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以DM9000芯片为例。该芯片的硬件结构为：

重要构成有MAC、PHY、MII。将这几部分抽象成相应的网络模型层，为：

其中MAC属于数据链路层，PHY属于物理层。

MAC主要负责数据帧的构建、数据差错检查、传送控制等。当网络协议栈发送IP数据包过来时，MAC对其进行封装成以太网包，然后发送到PHY。

PHY是物理接口收发器，属于物理层，当它收到MAC过来的数据时，它会去加上校验码，然后按照物理层的规则进行数据编码，再发送到传输介质上。接收时则过程相反。

MII是媒体独立接口，“媒体独立”表明MAC一定的情况下，任何类型的PHY设备都可以正常工作。

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DM9000内部都多个寄存器，但它只开放index端口和数据端口，即我们不能直接通过地址访问它的寄存器，只能通过这两个端口间接地访问它的寄存器。其中index端口用于写入偏移量，数据端口用于写入数值。对DM9000进行操作，首先要进行正确的寻址，AEN指地址允许，是输入引脚片选信号。DM9000的基地址是由TXD[3:0]和SA4~SA9组成，当AEN低电平，SA9和SA8高电平，SA7~SA4低电平时，则选中DM9000。默认地址为300H。在S3C2440中，index端口地址为0x20000300，数据端口地址为0x20000304。从DM9000的引脚图可以看出，index端口和数据端口使用的都是SD0~SD15，功能区分是依靠CMD引脚的电平区分。当CMD=1时，SD0~SD15用于数据端口；当CMD=0时，SD0~SD15用于index端口。这是index端口与数据端口地址差异的来源。当地址为0x20000300时，CMD=0；当地址为0x20000304时，CMD=1.

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编写网卡驱动，可移植uboot程序，即参考并修改uboot程序，主要实现的功能有：

①网卡初始化 ②数据包的收发

其中网卡初始化的步骤为：

①设置片选，即设置网卡所在的bank4的相关寄存器（参考内存初始化） ②中断初始化（数据包的接收是通过中断触发） ③复位设备 ④捕获DM9000 ⑤MAC初始化 ⑥填充MAC地址 ⑦激活DM9000

数据包的发送步骤如下：

①禁止中断（可避免干扰，发送完毕再开启中断） ②写入发送数据的长度 ③写入待发送的数据 ④启动发送 ⑤等待发送完毕 ⑥清除发送状态 ⑦恢复中断

数据包的接收步骤如下：

①判断是否产生中断，且清除中断状态位 ②空读 ③读取状态 ④读取包的长度 ⑤读取包的数据 ⑥设置中断（使中断产生时能进入数据包接收函数，并清除中断的相关状态寄存器）

代码（需要结合ARP协议一节）为:

#include "dm9000.h"#include "arp.h"#define DM_ADD (*((volatile unsigned short *)0x20000300))#define DM_DAT (*((volatile unsigned short *)0x20000304))#define GPFCON    (*(volatile unsigned *)0x56000050)    //Port F control#define EXTINT0   (*(volatile unsigned *)0x56000088)    //External interrupt control register 0#define EINTMASK  (*(volatile unsigned *)0x560000a4)    //External interrupt mask#define SRCPND     (*(volatile unsigned *)0x4a000000)   //Interrupt request status#define INTPND     (*(volatile unsigned *)0x4a000010)   //Interrupt request status#define INTMSK     (*(volatile unsigned *)0x4a000008)   //Interrupt mask control#define EINTPEND  (*(volatile unsigned *)0x560000a8)    //External interrupt pending#define BWSCON    (*(volatile unsigned *)0x48000000)    //Bus width & wait status#define BANKCON4  (*(volatile unsigned *)0x48000014)    //BANK4 controlu8 *buffer = &arpbuf;u8 host_mac_addr[6] = {
  0xff,0xff,0xff,0xff,0xff,0xff};u8 mac_addr[6] = {
  9,8,7,6,5,4};u8 ip_addr[4] = {
  192,168,1,30};u8 host_ip_addr[4] = {
  192,168,1,100};u16 packet_len;void cs_init(){    BWSCON = BWSCON & (~(0x3<<16));    BWSCON = BWSCON |(0x1<<16);    BANKCON4 = (0x0<<13)|(0x0<<11)|(0x7<<8)|(0x1<<6)|(0x0<<4)|(0x0<<2)|(0x0<<0);}void int_init(){    GPFCON = GPFCON &(~(0x3<<14));    GPFCON = GPFCON |(0x2<<14);    EXTINT0 = EXTINT0 & (~(0x7<<28));    EXTINT0 = EXTINT0 | (0x1<<28);    INTMSK = INTMSK &(~(1<<4));    EINTMASK = EINTMASK & (~(0x1<<7));    SRCPND = (1<<4);    INTPND = (1<<4);}void dm9000_reg_write(u16 reg,u16 data){    DM_ADD = reg;       DM_DAT = data;  }u8 dm9000_reg_read(u16 reg){    DM_ADD = reg;    return DM_DAT;  }void dm9000_reset(){    dm9000_reg_write(DM9000_GPCR, GPCR_GPIO0_OUT);    dm9000_reg_write(DM9000_GPR, 0);        dm9000_reg_write(DM9000_NCR, (NCR_LBK_INT_MAC | NCR_RST));    dm9000_reg_write(DM9000_NCR, 0);    dm9000_reg_write(DM9000_NCR, (NCR_LBK_INT_MAC | NCR_RST));    dm9000_reg_write(DM9000_NCR, 0);}void dm9000_probe(void){    u32 id_val;    id_val = dm9000_reg_read(DM9000_VIDL);    id_val |= dm9000_reg_read(DM9000_VIDH) << 8;    id_val |= dm9000_reg_read(DM9000_PIDL) << 16;    id_val |= dm9000_reg_read(DM9000_PIDH) << 24;    if (id_val == DM9000_ID) {        printf("dm9000 is found !\n");        return ;    } else {        printf("dm9000 is not found !\n");        return ;    }}void dm9000_init(){    u32 i;    /*设置片选*/    cs_init();    /*中断初始化*/    int_init();    /*复位设备*/    dm9000_reset();    /*捕获dm9000*/    dm9000_probe();    /*MAC初始化*/    /* Program operating register, only internal phy supported */    dm9000_reg_write(DM9000_NCR, 0x0);    /* TX Polling clear */    dm9000_reg_write(DM9000_TCR, 0);    /* Less 3Kb, 200us */    dm9000_reg_write(DM9000_BPTR, BPTR_BPHW(3) | BPTR_JPT_600US);    /* Flow Control : High/Low Water */    dm9000_reg_write(DM9000_FCTR, FCTR_HWOT(3) | FCTR_LWOT(8));    /* SH FIXME: This looks strange! Flow Control */    dm9000_reg_write(DM9000_FCR, 0x0);    /* Special Mode */    dm9000_reg_write(DM9000_SMCR, 0);    /* clear TX status */    dm9000_reg_write(DM9000_NSR, NSR_WAKEST | NSR_TX2END | NSR_TX1END);    /* Clear interrupt status */    dm9000_reg_write(DM9000_ISR, ISR_ROOS | ISR_ROS | ISR_PTS | ISR_PRS);    /*填充MAC地址*/    for (i = 0; i < 6; i++)        dm9000_reg_write(DM9000_PAR+i, mac_addr[i]);    /*激活DM9000*/        dm9000_reg_write(DM9000_RCR, RCR_DIS_LONG | RCR_DIS_CRC | RCR_RXEN);    /* Enable TX/RX interrupt mask */    dm9000_reg_write(DM9000_IMR, IMR_PAR);}void dm9000_tx(u8 *data,u32 length){    u32 i;    /*禁止中断*/    dm9000_reg_write(DM9000_IMR,0x80);    /*写入发送数据的长度*/    dm9000_reg_write(DM9000_TXPLL, length & 0xff);    dm9000_reg_write(DM9000_TXPLH, (length >> 8) & 0xff);    /*写入待发送的数据*/    DM_ADD = DM9000_MWCMD;    for(i=0;i
   
    >8)&0x0ff;       }    }    return len;}void int_issue(){    packet_len = dm9000_rx(buffer);     arp_process();    SRCPND = (1<<4);    INTPND = (1<<4);    EINTPEND |= 1<<7; }